Delta-Sigma fractional N frequency synthesizers provide low phase noise, fast channel switching speed and fine frequency resolution simultaneously. The Delta-Sigma Modulator (DSM) is a key component which is used to control a programmable divider in a phase locked loop (PLL) to achieve fractional division. The input to the DSM is a digital word representing the fractional portion of the desired division ration. The output is a single-bit or multi-bit stream with an average equal to the fractional value of the input to the DSM and high-pass filtered quantization noise. The high frequency quantization error in the bit stream is converted to high frequency phase error in the PLL. In a well designed loop this high frequency noise is filtered out by the low-pass filtering function of the closed loop.
Compared with integer N frequency synthesizers, delta sigma fractional N synthesizers, however, have two drawbacks: additional silicon area and current consumption due to the presence of a delta sigma modulator and quantization noise injected into the PLL collectively by the divider and the delta sigma modulator. The quantization noise may consist of only discrete tones with large amplitude. In the time-domain, the same problem manifests itself as short sequence length. This originates from the fact that a DSM with a dc input is a digital state machine with a finite number of possible states. Such a problem is especially the case when the number of bits in the accumulators forming the DSM is small. The minimum bit number is determined by the synthesizer frequency resolution specification. For GSM, where the reference frequency is 13 MHz and the frequency resolution is 200 kHz, the minimum number of bits is 7. A DSM with such a small bit number would usually exhibit high discrete tones in its output spectrum for most inputs. Traditionally, the accumulators in such DSMs have been modulo power-of-2 accumulators since binary arithmetic is simpler to implement in digital logic.